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Jesse Barnes | 14 Jun 2012 20:20
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[PATCH 01/10] drm/i915: ValleyView mode setting limits and PLL functions

Add some VLV limit structures and update the PLL code.

v2: resolve conflicts, Vijay to re-post with PLL valid checks and fixed limits
v3: re-add dpio write function

Signed-off-by: Shobhit Kumar <shobhit.kumar <at> intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman <at> intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    1 +
 drivers/gpu/drm/i915/intel_display.c |  250 +++++++++++++++++++++++++++++++++-
 2 files changed, 249 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7dcc04f..281446d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
 <at>  <at>  -900,6 +900,7  <at>  <at> 
 #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
+#define   DPLL_LOCK_VLV			(1<<15)
 #define   DPLL_INTEGRATED_CLOCK_VLV	(1<<13)

 #define SRX_INDEX		0x3c4
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0161d94..5006928 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
 <at>  <at>  -98,6 +98,11  <at>  <at>  intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 			   int target, int refclk, intel_clock_t *match_clock,
(Continue reading)

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headers
Jesse Barnes | 14 Jun 2012 20:20
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[PATCH 02/10] drm/i915: Enable DP panel power sequencing for ValleyView

From: Shobhit Kumar <shobhit.kumar <at> intel.com>

VLV supports two dp panels, there are two set of panel power sequence
registers which needed to be programmed based on the configured
pipe. This patch add supports for the same

Acked-by: Acked-by: Ben Widawsky <ben <at> bwidawsk.net>
Signed-off-by: Beeresh G <beeresh.g <at> intel.com>
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman <at> intel.com>
Reviewed-by: Jesse Barnes <jesse.barnes <at> intel.com>
Signed-off-by: Jesse Barnes <jbarnes <at> virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h |   12 ++++++++++++
 drivers/gpu/drm/i915/intel_dp.c |    8 +++++++-
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 281446d..a9e9d92 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
 <at>  <at>  -3854,6 +3854,18  <at>  <at> 

 #define BLC_PWM_PCH_CTL2	0xc8254

+#define PIPEA_PP_STATUS         0x61200
+#define PIPEA_PP_CONTROL        0x61204
+#define PIPEA_PP_ON_DELAYS      0x61208
+#define PIPEA_PP_OFF_DELAYS     0x6120c
+#define PIPEA_PP_DIVISOR        0x61210
+
(Continue reading)

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headers
Jesse Barnes | 14 Jun 2012 20:20
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[PATCH 03/10] drm/i915: add ValleyView specific CRT detect function

Might be able to merge this back in at some point, but we're seeing bugs
with ADPA based detection, so keep it separate for now with explicit
hotplug trigger usage.

v2: drop superfluous debug message
v3: comment forced detection, need to debug (Eugeni)

Reviewed-by: Eugeni Dodonov <eugeni.dodonov <at> intel.com>
Signed-off-by: Jesse Barnes <jbarnes <at> virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_crt.c |   39 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 75a70c4..1333a65 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
 <at>  <at>  -230,6 +230,42  <at>  <at>  static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 	return ret;
 }

+static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
+{
+	struct drm_device *dev = connector->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 adpa;
+	bool ret;
+	u32 save_adpa;
+
+	save_adpa = adpa = I915_READ(ADPA);
(Continue reading)

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headers
Jesse Barnes | 14 Jun 2012 20:20
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[PATCH 04/10] drm/i915: add HDMI and DP port enumeration on ValleyView

ValleyView is similar to IbexPeak here, but with different register
offsets.

v2: use SDVOB instead ov VLV_HDMIB (Daniel)
    drop unnecessary eDP check in DP_C init (Daniel)

eDP support will be coming later from Shobit.

Signed-off-by: Jesse Barnes <jbarnes <at> virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h      |    1 -
 drivers/gpu/drm/i915/intel_display.c |   17 +++++++++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a9e9d92..263b50c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
 <at>  <at>  -3808,7 +3808,6  <at>  <at> 
 #define  ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)

 /* or SDVOB */
-#define VLV_HDMIB 0x61140
 #define HDMIB   0xe1140
 #define  PORT_ENABLE    (1 << 31)
 #define  TRANSCODER(pipe)       ((pipe) << 30)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5006928..157dcb0a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
(Continue reading)

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headers
Jesse Barnes | 14 Jun 2012 20:20
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[PATCH 05/10] drm/i915: access VLV regs through read/write switch

Since the offsets have all moved around.

Signed-off-by: Jesse Barnes <jbarnes <at> virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |   80 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 78 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 238a521..747dc8d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
 <at>  <at>  -1144,6 +1144,77  <at>  <at>  MODULE_LICENSE("GPL and additional rights");
         ((reg) != FORCEWAKE)) && \
        (!IS_VALLEYVIEW((dev_priv)->dev))

+static bool IS_DISPLAYREG(u32 reg)
+{
+	if (reg >= RENDER_RING_BASE &&
+	    reg < RENDER_RING_BASE + 0xff)
+		return false;
+	if (reg >= GEN6_BSD_RING_BASE &&
+	    reg < GEN6_BSD_RING_BASE + 0xff)
+		return false;
+	if (reg >= BLT_RING_BASE &&
+	    reg < BLT_RING_BASE + 0xff)
+		return false;
+
+	if (reg == PGTBL_ER)
+		return false;
+
(Continue reading)

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headers
Jesse Barnes | 14 Jun 2012 20:20
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[PATCH 09/10] drm/i915: enable display messages to GT on ValleyView

Signed-off-by: Jesse Barnes <jbarnes <at> virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_pm.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d0ce2a5..4fa1a78 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
 <at>  <at>  -3474,6 +3474,13  <at>  <at>  static void valleyview_init_clock_gating(struct drm_device *dev)

 	I915_WRITE(CACHE_MODE_1,
 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
+
+	/*
+	 * On ValleyView, the GUnit needs to signal the GT
+	 * when flip and other events complete.  So enable
+	 * all the GUnit->GT interrupts here
+	 */
+	I915_WRITE(VLV_DPFLIPSTAT, 0x3f7f0000);
 }

 static void g4x_init_clock_gating(struct drm_device *dev)
--

-- 
1.7.9.5
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headers
Jesse Barnes | 14 Jun 2012 20:20
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[PATCH 06/10] drm/i915: VLV VGA port only handles on & off, like PCH VGA

Signed-off-by: Jesse Barnes <jbarnes <at> virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_crt.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 1333a65..ac62f24 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
 <at>  <at>  -88,6 +88,9  <at>  <at>  static void gmch_crt_dpms(struct drm_encoder *encoder, int mode)
 	temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 	temp &= ~ADPA_DAC_ENABLE;

+	if (IS_VALLEYVIEW(dev) && mode != DRM_MODE_DPMS_ON)
+		mode = DRM_MODE_DPMS_OFF;
+
 	switch (mode) {
 	case DRM_MODE_DPMS_ON:
 		temp |= ADPA_DAC_ENABLE;
--

-- 
1.7.9.5
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headers
Jesse Barnes | 14 Jun 2012 20:20
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[PATCH 08/10] drm/i915: support page flipping on ValleyView

And restructure the IRQ handling a little.  We can use pipestat for most
things, and make sure we don't affect pipe events when enabling and
disabling vblank interupts.

Signed-off-by: Jesse Barnes <jbarnes <at> virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_irq.c |   62 +++++++++++++++++----------------------
 1 file changed, 27 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0e87664..453ea7c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
 <at>  <at>  -513,15 +513,10  <at>  <at>  static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
 	unsigned long irqflags;
 	int pipe;
 	u32 pipe_stats[I915_MAX_PIPES];
-	u32 vblank_status;
-	int vblank = 0;
 	bool blc_event;

 	atomic_inc(&dev_priv->irq_received);

-	vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
-		PIPE_VBLANK_INTERRUPT_STATUS;
-
 	while (true) {
 		iir = I915_READ(VLV_IIR);
 		gt_iir = I915_READ(GTIIR);
 <at>  <at>  -551,6 +546,16  <at>  <at>  static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
(Continue reading)

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headers
Jesse Barnes | 14 Jun 2012 20:20
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[PATCH 07/10] agp/intel: allow cacheable and GDFT PTEs on ValleyView

The PTE format is similar to SNB, but we don't support an MLC and don't
need chipset flushing.

Signed-off-by: Jesse Barnes <jbarnes <at> virtuousgeek.org>
---
 drivers/char/agp/intel-gtt.c |   11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 1237e75..c1e2943 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
 <at>  <at>  -1182,9 +1182,17  <at>  <at>  static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
 static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,
 				   unsigned int flags)
 {
+	unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
+	unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
 	u32 pte_flags;

-	pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
+	if (type_mask == AGP_USER_MEMORY)
+		pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
+	else {
+		pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
+		if (gfdt)
+			pte_flags |= GEN6_PTE_GFDT;
+	}

 	/* gen6 has bit11-4 for physical addr bit39-32 */
(Continue reading)

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headers
Jesse Barnes | 14 Jun 2012 20:20
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[PATCH 10/10] drm/i915: bind driver to ValleyView chipsets

With the code in place, we can bind the driver, should make bisect possible.

Signed-off-by: Jesse Barnes <jbarnes <at> virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 747dc8d..8bdb000 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
 <at>  <at>  -352,6 +352,9  <at>  <at>  static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 	INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 	INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
+	INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
+	INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
+	INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 	{0, 0, 0}
 };

--

-- 
1.7.9.5
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