Re: [PIC] Software PLL using a dsPIC30F series chip...

Antonio L. Benci (by way of Barry Gershenfeld) wrote:
> [Just a guess, that a PIC tag will net you more responses] -- Barry
> * *
> 

Sigh. I already replied once to this, but with all your email troubles, you
must have missed it.

Antonio L. Benci wrote:
> I'm stuck...
> 
> I have been asked to develop a digital PLL, using a micro, dsPIC in this 
> case. Using a reference clk of 10MHz to derive an 80MHz clk. Corrections 
> within the loop will be 250nS discrete time jumps.

What does that mean? 250 ns is 20 cycles of 80 MHz. How can you build a PLL
on that basis?

Perhaps you should draw us a block diagram of what you have in mind. Show
which functions would be in hardware and which in software.

I have a lot of experience with PLLs -- analog, digital, hybrid -- using
both FPGAs and DSPs (many years in the telecom business). If I can figure
out where you want to go with this, I can probably help out.

I don't know if it's relevant, but I also have an article in the works for
Circuit Cellar about building a software timebase for embedded firmware
that's precisely synchronized to an external reference. But that probably
won't appear until early 2009.