Milkymist MMU making progress

Hello Milkymisters (and milkymadams),

I'm proud to announce that the Milkymist MMU is making small progresses :)
It seems that phase 2 is in a good shape: it passes a few tests [0] in
ISim simulation as well as on real FPGA running MMU-enabled Milkymist SoC

Phase 2 was "allow MMU to generate a CPU exception upon a page fault".

The use case scenario is as follow :

The Operating System (Linux/RTEMS) keeps - somewhere in memory (DDR
SDRAM) - all virtual to physical memory mappings.
A small subset of those mappings is also stored in on-chip FPGA memory
in the TLB (Translation Lookaside Buffer [1]).
The TLB is a cache to speed up virtual address translations.

When MMU is enabled (in a Linux user space process for example), TLB is
checked on every memory load/store.
If the virtual address being accessed has it's physical page frame
number stored in the TLB then the translation is instantaneous.
If the mapping is not in the TLB, then MMU cannot translate it, it
therefore generates a CPU exception.

This exception makes the CPU run the "page fault handler" [2], a piece
of code which will walk through previously described virtual to physical
mappings stored in DDR SDRAM.
If the virtual address responsible for the page fault is indeed mapped
to a physical address, the page fault handler will find it, update the
TLB with this piece of information and then return to the code which
caused the page fault.