problems with 48 bit instruction architecture...

I'm looking at a machine with 48 bit instructions (fixed length).  I'm hosting on Ubuntu x86 linux.

The target architecture is  little-endian, and I've described the machine with

     (define-arch
           ....
          (default-alignment aligned)
          (insn-lsb0? #t)
          (machs  xyz)
          (isas xyz))

    (define-isa (name xyz)
           (default-insn-word-bitsize 48)
           (default-insn-bitsize 48)
           (base-insn-bitsize 48))

and then defined the fields of the instruction beginning at bit 47, the MSB of what should be byte 0 of a 6 byte instruction.

BUT, when I run cgen, I find that my xyz-opc.c file gets compilation errors because the CGEN_IFMT entries
are being given
hex literals like 

        oxfc0000000000

which won't fit into the CGEN_INSN_INT type field (because that's defined as 'int' in cgen.h.  If I change
cgen.h to have CGEN_INSN_INT defined as uint64, then my opcodes stuff all compiles and the assembler
builds.  But the generated .o
file has the instruction bytes output (according to objdump) for a "ret 4" instruction comes out as

   0000    0400c200 0000