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Nir Tzachar | 1 Jan 2004 12:51
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Re: synchronization without hardware support

> On Thu, Jan 01, 2004 at 08:51:35AM +0200, Nir Tzachar wrote:
> > > those generally fall apart if the cpu also has a cpu store buffer and a
> > > weakly ordered memory model ;)
> > if you referred to one of the mentioned algorithms, can you please explain?
> 
> a cpu with a store buffer and a weakly ordered memory model will not have
> it's writes to memory visible to other cpus without explicit
> synchronisation...... 

ok, got it. but hey, if ur cpu has a store buffer or uses a weakly 
ordered memory model, then you also got some synchronization primitives, 
(ie; memory barriers, which can be used to implement a higher 
synchronization primitive) no? otherwise, the cpu manufacturer has done a 
pretty bad job....

anyway, if his cpu does not implement any synchronization primitives, then 
he got a uni-processor box (very likely.. ), and all his problems can be 
solved with one of these algorithms.

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nir.
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Alexander Nyberg | 23 Feb 2004 22:18
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init/do_mounts.c : try_name()

I'm quite curious over where read() & open() are defined, as no FS is
yet mounted there can be no fs specific read() & open() right?
Are they wrappers for do_read or sys_read? I couldn't find them at least
(yes I have lxr'ed).

Thanks,
Alex

static dev_t __init try_name(char *name, int part)
56 {
57         char path[64];
58         char buf[32];
59         int range;
60         dev_t res;
61         char *s;
62         int len;
63         int fd;
64         unsigned int maj, min;
65
66         /* read device number from .../dev */
67
68         sprintf(path, "/sys/block/%s/dev", name);
69         fd = open(path, 0, 0);
70         if (fd < 0)
71                 goto fail;
72         len = read(fd, buf, 32);
73         close(fd);

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Ameet Gandhare | 9 Jan 2004 11:04

Re: synchronization without hardware support

I think Leslie Lamport has developed Bakery Algorithm which does not 
need any h/w support for synchronization.
Regards,
Ameet
Nir Tzachar wrote:
>>On Thu, Jan 01, 2004 at 08:51:35AM +0200, Nir Tzachar wrote:
>>
>>>>those generally fall apart if the cpu also has a cpu store buffer and a
>>>>weakly ordered memory model ;)
>>>
>>>if you referred to one of the mentioned algorithms, can you please explain?
>>
>>a cpu with a store buffer and a weakly ordered memory model will not have
>>it's writes to memory visible to other cpus without explicit
>>synchronisation...... 
> 
> 
> ok, got it. but hey, if ur cpu has a store buffer or uses a weakly 
> ordered memory model, then you also got some synchronization primitives, 
> (ie; memory barriers, which can be used to implement a higher 
> synchronization primitive) no? otherwise, the cpu manufacturer has done a 
> pretty bad job....
> 
> anyway, if his cpu does not implement any synchronization primitives, then 
> he got a uni-processor box (very likely.. ), and all his problems can be 
> solved with one of these algorithms.
> 
>  -- 
> ========================================================================
> nir.
(Continue reading)

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Gmane