Re: Vref_DQ Vref_CA VTT decoupling in DDR3 DIMM

Statement: VTT, Minimum of one decoupling capacitor to VDD per every two 
termination resistors

Question: Why VTT decoupling capacitor to VDD not VSS(usually GND)? will this increase noise coupling
between VTT and VDD?

Ans: Here the answer is hiding in the requirement "per every two 
termination resistor" , the fact is VDDQ is "decoupled" w.r. to VTT 
instead of VSS. The reason is When high side mosfet of the buffer is  
turned ON, for logic HI, the current flow is from VDDQ to mosfet to 
Termination Resistor to VTT power supply. Signal is switched w.r.t. 
VTT,  So we need to decouple the Buffer's VDDQ pin to VTT, not to VDD.
No need for the decap btw Buffer's VSS to VTT , because VSS is much more 
robust than VDDQ to supply necessary instantaneous current for logic LOW.

Goal is to dump the noise to reference right, there is no worry of noise 
coupling between VTT and VDDQ

Decoupling Vref depends on how Vref is generated, decoupled usually 
w.r.t GND. There is also a idea about connecting a cap to VDD from 
Vref.  So any variation in the VDD is tracked by Vref. Here the need and 
size of cap matters and need to be ascertained during DVT.

In Tesla' situation it is better to ask DRAM vendor, they know their 
internal buffers read circuit implementation.
May be Vref w.r.t to +ve or -ve i/p of opAmp.  I feel this requirement 
is DRAM driven than a layout driven choice.
As matter of fact, any layout recommendation from vendor data sheet 
should not be blindly followed and situation varies.