(electronic) signal integrity list ()

Prashanth Rajappan | 8 Aug 2012 15:32

10 Layer Stackup Recommendation for Board with High speed Signals(SERDES/DDR)

Hi All,
I am looking for suggestions for our PCB which has high speed interfaces like SERDES /DDR2/GIGA BIT
Ethernet.The current stackup  is given below.

Top
GND 
SIG1 - SERDES / DDR2/High Speed Signals
SIG2 - DDR2
POWER1
GND
SIG3 - DDR2
SIG4 - SERDES / DDR2/High SpeedSignals
POWER2
BOT

PLease let me know your comments or suggestion regarding the same.

Thank you in advance!

Regards
Prasanth

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steve weir | 8 Aug 2012 19:46

Re: 10 Layer Stackup Recommendation for Board with High speed Signals(SERDES/DDR)

That stack-up could be in real trouble:  Big cavities, plus lot's of 
single-ended injection usually spells trouble.  If you plan to route the 
DDR2 Manhattan using L3 and L8 as a routing pair, then about your only 
hope is if you forgo Power2 and make that also GND.  Otherwise, 
something will have to give.

Steve
On 8/8/2012 6:32 AM, Prashanth Rajappan wrote:
> Hi All,
> I am looking for suggestions for our PCB which has high speed interfaces like SERDES /DDR2/GIGA BIT
Ethernet.The current stackup  is given below.
>
> Top
> GND
> SIG1 - SERDES / DDR2/High Speed Signals
> SIG2 - DDR2
> POWER1
> GND
> SIG3 - DDR2
> SIG4 - SERDES / DDR2/High SpeedSignals
> POWER2
> BOT
>
> PLease let me know your comments or suggestion regarding the same.
>
> Thank you in advance!
>
>
> Regards
> Prasanth

(Continue reading)

headers

Jory McKinley | 8 Aug 2012 20:21

Re: 10 Layer Stackup Recommendation for Board with High speed Signals(SERDES/DDR)

How about this:
TOP/GND
SPLIT PWR1/2
GND
SIG1 - SERDES / DDR2/High Speed Signals 

SIG2 - DDR2 

GND
SIG3 - DDR2
SIG4 - SERDES / DDR2/High SpeedSignals
GND/ISOLATED PWR (covered by bottom ground and no signal reference)
BOTTOM/GND

 
Jory McKinley
McKinley Consulting
e-mail: jory_mckinley@...
phone: (774)-285-2859

________________________________
 From: steve weir <weirsi@...>
To: si-list@... 
Sent: Wednesday, August 8, 2012 1:46 PM
Subject: [SI-LIST] Re: 10 Layer Stackup Recommendation for Board with High speed Signals(SERDES/DDR)

That stack-up could be in real trouble:  Big cavities, plus lot's of 
single-ended injection usually spells trouble.  If you plan to route the 
DDR2 Manhattan using L3 and L8 as a routing pair, then about your only 
hope is if you forgo Power2 and make that also GND.  Otherwise,

(Continue reading)

headers

Joel Brown | 8 Aug 2012 20:40

Re: 10 Layer Stackup Recommendation for Board with High speed Signals(SERDES/DDR)

I understand that having the power near the outer layers reduces inductance
of the PDN.
But this is how we would typically do it:
Top
GND
SIG1 - SERDES / DDR2/High Speed Signals
SIG2 - DDR2
GND
POWER1
POWER2
GND
SIG3 - DDR2
SIG4 - SERDES / DDR2/High SpeedSignals
GND
BOT

On Wed, Aug 8, 2012 at 11:21 AM, Jory McKinley <jory_mckinley@...>wrote:

> How about this:
> TOP/GND
> SPLIT PWR1/2
> GND
> SIG1 - SERDES / DDR2/High Speed Signals
>
> SIG2 - DDR2
>
> GND
> SIG3 - DDR2
> SIG4 - SERDES / DDR2/High SpeedSignals
> GND/ISOLATED PWR (covered by bottom ground and no signal reference)

(Continue reading)

headers

steve weir | 8 Aug 2012 21:25

Re: 10 Layer Stackup Recommendation for Board with High speed Signals(SERDES/DDR)

If you can tolerate the impact on power delivery, that 12 layer stack-up 
works.  It requires about 3X the number of bypass capacitors as the 
other stack-up for the same impedance.  What you get out of it is core 
between the S / G layers which has better thickness control than 
prepreg.  You also get Vss reference on all routing layers.
Steve.
On 8/8/2012 11:40 AM, Joel Brown wrote:
> I understand that having the power near the outer layers reduces 
> inductance of the PDN.
> But this is how we would typically do it:
>
> Top
> GND
> SIG1 - SERDES / DDR2/High Speed Signals
> SIG2 - DDR2
> GND
> POWER1
> POWER2
> GND
> SIG3 - DDR2
> SIG4 - SERDES / DDR2/High SpeedSignals
> GND
> BOT
>
> On Wed, Aug 8, 2012 at 11:21 AM, Jory McKinley 
> <jory_mckinley@...
<mailto:jory_mckinley@...>> wrote:
>
>     How about this:
>     TOP/GND

(Continue reading)

headers

steve weir | 8 Aug 2012 21:20

Re: 10 Layer Stackup Recommendation for Board with High speed Signals(SERDES/DDR)

There are a couple of problems:
1. Unbalanced construction
2. The top could be useless as a plane depending on what and how many 
parts are used.

Best Regards,

Steve.
On 8/8/2012 11:21 AM, Jory McKinley wrote:
> How about this:
>
> TOP/GND
> SPLIT PWR1/2
> GND
> SIG1 - SERDES / DDR2/High Speed Signals
> SIG2 - DDR2
> GND
> SIG3 - DDR2
> SIG4 - SERDES / DDR2/High SpeedSignals
> GND/ISOLATED PWR (covered by bottom ground and no signal reference)
> BOTTOM/GND
>
>
>
>
> Jory McKinley
> McKinley Consulting
> e-mail: jory_mckinley@...
> phone: (774)-285-2859
> ------------------------------------------------------------------------

(Continue reading)

headers

Jory McKinley | 8 Aug 2012 22:29

Re: 10 Layer Stackup Recommendation for Board with High speed Signals(SERDES/DDR)

Unbalanced not so good for yield in keeping with 10-layers only lets try, with the core being double thick
(between PWR1 and PWR2) not ideal due to decoupling/cavity but with core and good z-direction stitch will
provide signal isolation for limit of layers.
TOP/GND
SIG1 - SERDES / DDR2/High Speed Signals 
SIG2 - DDR2
GND
PWR 1
PWR 2
GND
SIG3 - DDR2
SIG4 - SERDES / DDR2/High SpeedSignals
BOTTOM/GND

________________________________
 From: steve weir <weirsi@...>
To: Jory McKinley <jory_mckinley@...> 
Cc: "si-list@..."
<si-list@...> 
Sent: Wednesday, August 8, 2012 3:20 PM
Subject: Re: [SI-LIST] Re: 10 Layer Stackup Recommendation for Board with High speed Signals(SERDES/DDR)

There are a couple of problems:

1. Unbalanced construction
2. The top could be useless as a plane depending on what and how
      many parts are used.

Best Regards,

(Continue reading)

headers

Bill Hargin (ICD | 8 Aug 2012 22:19

Re: 10 Layer Stackup Recommendation for Board with High speed Signals(SERDES/DDR)

Hi Prashanth:

Without having more details, it's probably going to be difficult for someone
on the outside to provide helpful advice here, but here are some general
observations.  

The first thing you need to do is nail down how many routing layers you're
going to need.  It's not clear what you're planning to do with the top and
bottom layers, or how many layers you need.  If you can fit some of your
SERDES signals on those layers, for example - close to the BGAs - that might
not be a bad idea.

Once that's determined - e.g., whether you need 4 or 6 signal layers - you
can start distributing your power and ground planes.  It's not a bad idea to
put ground planes near the surface to avoid coupling between power planes
and mounting pads on the top and bottom.  At the speeds you're working with,
you might benefit from some power/ground plane capacitance, to pull your PDN
impedance down at higher frequencies.  So, mean 4 or 6 signal layers, your 2
power planes, plus 2 ground planes ... Something like this:

4 Signal Layers:  
1 - SIG1 - SERDES / DDR2/High Speed Signals
2 - GND 
3 - POWER1
4 - SIG2 - DDR2
5 - SIG3 - DDR2 (Pay attn.. to broadside coupling/parallelism on L4-L5.)
6 - POWER2
7 - GND
8 - SIG4 - SERDES / DDR2/High SpeedSignals

(Continue reading)

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steve weir | 9 Aug 2012 02:33

Re: 10 Layer Stackup Recommendation for Board with High speed Signals(SERDES/DDR)

Bill, as you noted lack of detailed information on the requirements 
makes the trade-offs difficult to assess. My bottom line is: A 10 layer 
board is aggressive for a system that requires two power layers and at 
least 2 DDR2 data layers, and at least 4 signal routing layers overall. 
Depending on what's available to trade a very experienced engineer may 
be able to work out a viable design. An inexperienced engineer is 
unlikely to make an aggressive design work due to Scott McMorrow's 
infamous "whack-a-mole" syndrome: solve one problem and it creates another.

Best Regards,

Steve.

On 8/8/2012 1:19 PM, Bill Hargin (ICD) wrote:
> Hi Prashanth:
>
> Without having more details, it's probably going to be difficult for someone
> on the outside to provide helpful advice here, but here are some general
> observations.
>
> The first thing you need to do is nail down how many routing layers you're
> going to need.  It's not clear what you're planning to do with the top and
> bottom layers, or how many layers you need.  If you can fit some of your
> SERDES signals on those layers, for example - close to the BGAs - that might
> not be a bad idea.
>
> Once that's determined - e.g., whether you need 4 or 6 signal layers - you
> can start distributing your power and ground planes.  It's not a bad idea to
> put ground planes near the surface to avoid coupling between power planes
> and mounting pads on the top and bottom.  At the speeds you're working with,

(Continue reading)

headers

Prashanth Rajappan | 9 Aug 2012 16:17

Re: 10 Layer Stackup Recommendation for Board with High speed Signals(SERDES/DDR)

Hi All,
Thanks for the response.I have added more details as per suggestions .In the link given below ,basic block
diagram and the signal speeds(at max through put) have been given.

http://flickr.com/gp/84656325 <at> N08/jH23r1

My Layer constraint is 10 Layer.Â 

Bill w.r.t in the board ,one power goes to the entire board area hence it will take up the enitire power plane
.And in the other power plane we would require to provide multiple power signals hence splitting the
plane.Because of that we are not able to give continuous reference to the DDR or any other critical signals
with one power plane .

Also if we dont have much option to spread power over signal layers because of the routing space constraints.

Regarding SERDES signals,the tracks can be routed in TOP and Bottom Layers .Another issue is the length of
SERDES signal tracks .Now the manhattan length is coming to 150mm.

Ground pouring,we were planning to pour on top and bottom layers with enough spacing from the signals.
Is it wise to provide ground planes(as much as possible) in signal layers also.

Regards
Prasanth

________________________________
 From: Bill Hargin (ICD) <b.hargin@...>
To: prashanth_rajappan@...;
si-list@... 
Sent: Thursday, 9 August 2012 1:49 AM
Subject: [SI-LIST] Re: 10 Layer Stackup Recommendation for Board with High speed Signals(SERDES/DDR)

(Continue reading)

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steve weir | 9 Aug 2012 16:42

Re: 10 Layer Stackup Recommendation for Board with High speed Signals(SERDES/DDR)

The first constraint is that the design has to work. If you are going to 
make this design work in 10 layers, then you have significant effort in 
front of you. The stack-up that you started with does not look like a 
good starting point to me. If I were trying to shove 12 layers of stuff 
into a 10 layer board I would start with the premise that the board is a 
6 outer layer design:

T
G
HS1

x1
x2
x3
x4

HS2
G
B

If the high speed signals will all route with that constraint then I 
would work the composition and routing of the remaining four layers to 
distribute power and the low speed signals. That strategy may or may not 
succeed.

If I couldn't get the HS signals handled with this arrangement, then I 
would likely conclude that 10 layers will not be enough.

Steve.

(Continue reading)

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Nagy István | 9 Aug 2012 19:20

DF spec for PCB materials

Hi, I am trying to select a material for a few projects (small add-in cards as well as ATCA) that will support
10GBase-KR 10Gbps and similar signals.The better but still non-exotic materials datasheets all state
typical DF (loss tangent) values around 0.004-0.009, but all say spec value of 0.035 which is a lot higher.
I am guessing that the spec value may refer to the closest IPC slash sheet category?Do you work with typical
or spec DF values for your ~10Gbps board designs?What is the relevance of the two numbers for larger series
production? Regards,Istvan NagySr. Hardware Development EngineerFortinet, Sunnyvale CA

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Loyer, Jeff | 13 Aug 2012 17:24

Re: DF spec for PCB materials

I've never seen any other value than 0.035 specified as max Df.  I'm not sure what that ridiculous number
means - it seems senseless to me.  I pay attention to their "typical" values and use the 1GHz value, just to
keep it consistent (everyone quotes at least a 1GHz value).  Some other notes to control insertion loss on
PCB constructions:
* When trying to predict relative loss between materials, you might calculate sqrt(Er) * Df, rather than
only using Df; dielectric loss will be proportional to this.
* Be sure to specify either RTF or VLP; you can kill your low-loss material by using standard (HTE) copper
    * This may not help you with the microstrip traces - your supplier may insist on HTE copper for outer layers. 
Some suppliers can use RTF on outer layers.
       * Loss on outer layers is very hard to predict/model/control. If insertion loss is critical, you'll want to
stay on inner layers.  If you do use them, be sure to measure and monitor your insertion loss (see note below
on verifying insertion loss).
* Be sure to not allow aggressive Oxide Alternative (OA) adhesion treatments - they can also wreak havoc on
your insertion loss.
* You'll want to verify your actual insertion loss meets your expectations.  Many PCB suppliers are now
SET2DIL-capable and can measure the final product and report insertion loss (dB/inch) at 4 & 8 GHz.  That
will give you assurance that something hasn't been introduced that craters your insertion loss.
    * Once you find a "recipe" which meets your insertion loss requirements, you'll want to "lock down" that
recipe: specify that absolutely no changes are allowed unless you go through a requalification effort
(measuring insertion loss w/ the changes).

I hope this helps,
Jeff Loyer

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On Behalf Of Nagy István
Sent: Thursday, August 09, 2012 10:21 AM
To: si-list@...
Subject: [SI-LIST] DF spec for PCB materials

(Continue reading)

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Havermann, Gert | 13 Aug 2012 17:54

WG: Re: DF spec for PCB materials

The Specified Value is a maximum loss limit of every FR4 Material as per IPC. There are many mechanical and
electrical material properties a material has to fulfill to call it FR4, but I haven't seen any material
behaving soo bad that it fails these limits.
For the mechanical values like Peel strength the limit values allow comparing the properties with FR4. For
dk and df limits are easy to meet, and thus nonsens. Just go with what the manufacturer tells you is typical
for his product and don't pay much attention to the limits the IPC has put in place.

BR
Gert

----------------------------------------
Absender ist HARTING Electronics GmbH & Co. KG; Sitz der Gesellschaft: Espelkamp; Registergericht: Bad
Oeynhausen; Register-Nr.: HRA 5596; persönlich haftende Gesellschafterin: HARTING Electronics
Management GmbH; Sitz der Komplementär-GmbH: Espelkamp; Registergericht der Komplementär-GmbH:
Bad Oeynhausen; Register-Nr. der Komplementär-GmbH: HRB 8808; Geschäftsführer: Edgar-Peter
Duening, Torsten Ratzmann, Dr. Alexander Rost

-----Ursprüngliche Nachricht-----
Von: si-list-bounce@...
[mailto:si-list-bounce@...] Im Auftrag von Loyer, Jeff
Gesendet: Montag, 13. August 2012 17:25
An: buenos@...; si-list@...
Betreff: [SI-LIST] Re: DF spec for PCB materials

I've never seen any other value than 0.035 specified as max Df. I'm not sure what that ridiculous number
means - it seems senseless to me. I pay attention to their "typical" values and use the 1GHz value, just to
keep it consistent (everyone quotes at least a 1GHz value). Some other notes to control insertion loss on
PCB constructions:
* When trying to predict relative loss between materials, you might calculate sqrt(Er) * Df, rather than
only using Df; dielectric loss will be proportional to this.

(Continue reading)

headers

karthikeyavelan.kandasamy | 14 Aug 2012 07:55

Re: WG: Re: DF spec for PCB materials

Hi,

Megtron material has upto df=0.002 and we have used for Megtron-4  df=0.005 for our designs.
It may helpful you.

Regards
Karthik

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On Behalf Of Havermann, Gert
Sent: Monday, August 13, 2012 9:24 PM
To: si-list
Subject: [SI-LIST] WG: Re: DF spec for PCB materials

The Specified Value is a maximum loss limit of every FR4 Material as per IPC. There are many mechanical and
electrical material properties a material has to fulfill to call it FR4, but I haven't seen any material
behaving soo bad that it fails these limits.
For the mechanical values like Peel strength the limit values allow comparing the properties with FR4. For
dk and df limits are easy to meet, and thus nonsens. Just go with what the manufacturer tells you is typical
for his product and don't pay much attention to the limits the IPC has put in place.

BR
Gert

----------------------------------------
Absender ist HARTING Electronics GmbH & Co. KG; Sitz der Gesellschaft: Espelkamp; Registergericht: Bad
Oeynhausen; Register-Nr.: HRA 5596; persönlich haftende Gesellschafterin: HARTING Electronics
Management GmbH; Sitz der Komplementär-GmbH: Espelkamp; Registergericht der Komplementär-GmbH:
Bad Oeynhausen; Register-Nr. der Komplementär-GmbH: HRB 8808; Geschäftsführer: Edgar-Peter

(Continue reading)

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Istvan Nagy | 16 Aug 2012 05:48

Re: DF spec for PCB materials

Hi,

Thanks, actually it does help.
So I will focus on the typical value and try to get the FAB measure the loss 
per unit length.
Eric Bogatin had an article where he referred to you and intel's method 
about SET2DIL measurements.
Do you do this measurement on every batch of PCBs or every panel? On the 
same coupon as the impedance?
The other interesting thing is who pays for the manufactured panels where 
the loss does not meet the specified value... Often when a new type of 
requirement comes up, a lot of people especially at the fab try the 
requirement to look illegitimate or ridiculous. Wel, its a fight.
I will try to come up with some spec values for this.
I would not use microstrip for high speed, since all my designs are real 
products and very dense as well, unlike reference designs where they have a 
lot of space for routing on outer layers.
I am working with far east assembly company who is now standing between me 
and the PCB fab, so the communication channel for this issue seem to have 
too much dropped packets... I used to work at smaller companies in Europe, 
and always dealt with the fabs myself. Do you do it directly, or through 
another company, broker, other department...

Regards,
Istvan Nagy
Fortinet

-----Original Message----- 
From: Loyer, Jeff
Sent: Monday, August 13, 2012 8:24 AM

(Continue reading)

headers

Loyer, Jeff | 16 Aug 2012 17:06

Re: DF spec for PCB materials

Good questions, some of which we haven't worked out all the details for every design/vendor yet. But, I'll
try to clarify some things, based on what I've experienced.

Do you do this measurement on every batch of PCBs or every panel?
We have found that loss doesn't vary much between lots, so doesn't need to be measured at anywhere near the
frequency of impedance. Once you have found the recipe that gives adequate loss, it seems to hold steady.
Chu-tien (Jerry) Chia, Richard Kunze, David Boggs, and Margaret Cromley did an excellent paper on this
entitled "A Study of PCB Insertion Loss Variation in Manufacturing Using a New Low Cost Metrology",
available on the web. One thing we're finding on some stackups, however, is more variation, even between
layers within a stackup. For instance, on an 8 layer stackup, we have seen layers 3 and 6 have significantly
different loss (and/or coupling and/or propagation velocity!). We didn't note this previously, and are
working to understand it more.

On the same coupon as the impedance?
The SET2DIL coupon can be used to measure impedance, but we continue to have dedicated impedance coupons,
since they are much easier to measure quickly.

Who pays for the manufactured panels where the loss does not meet the specified value?
Ideally, it will be handled just like impedance, but that might be a bit optimistic at this point.
Currently, we typically go through some iterations with board vendors, building SET2DIL test boards
which mimic our proposed stackup and collaboratively modifying that stackup based on the SET2DIL
results. Once we find a "recipe" which meets our needs (with some tolerance), we "lock down" that recipe
and apply it to our product boards. Only a change in the recipe should cause the loss value to change
significantly, so I would think the fab vendor would be responsible at that point (though it hasn't been an
issue, as far as I know). Soon, we hope that vendors will have the tools and experience to be able to
predict/monitor/control loss before building boards (just as they predict impedance) and the onus will
fall to them to meet the loss requirement.

Often when a new type of requirement comes up, a lot of people especially at the fab try the requirement to
look illegitimate or ridiculous.

(Continue reading)

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Nagy István | 16 Aug 2012 21:05

Re: DF spec for PCB materials

Hi,
I think one thing might have been missed:
The DF variation between the batches (lots) of the manufactured raw PCB material sheets.
We and the mentioned articles were talking about batches of manufactured printed PCB boards.
I didn&#39;t find indication for anyone making sure that the PCB fab did/didn&#39;t order a new batch of
material between making two batches of printed PCBs for the same motherboard product. I think the fabs
keep larger stock of their few most usual materials, to guarantee lead time of their own product. This
stock might last for a very long time, maybe multiple batches of the same board design.

Right now I need to select materials for 10Gbps/signal. One of the big components we use has a design guide
stating channel loss requirement, I might apply the same numbers for other components running
interfaces at the same speed, although I know it&#39;s not really correct. If there is a difference in the
silicon IO requirements, it might be possible to adjust the loss requirement based on the difference in
electrical voltage level values in the datasheets. We can also calculate loss requirement for a total
channel (and divide it into segments) based on driver output voltage and receiver input voltage specs, as
I used to do it. I don&#39;t know how correct/incorrect that is.

Best regards,
Istvan Nagy
Sr. Hardware Development Engineer
Fortinet, Sunnyvale CA

-----Original Message-----
From: Loyer, Jeff
Sent: Thursday, August 16, 2012 8:06 AM
To: Istvan Nagy ; si-list@...
Subject: [SI-LIST] Re: DF spec for PCB materials

Good questions, some of which we haven&#39;t worked out all the details for every design/vendor yet.  But,
I&#39;ll try to clarify some things, based on what I&#39;ve experienced.

(Continue reading)

headers

Havermann, Gert | 17 Aug 2012 08:47

AW: Re: DF spec for PCB materials

Istvan,

the shelf life of PCB material isn't long at all. Cores last approx. 1 year, Prepregs only 3-6 months. Thats
why high speed materials have a long lead time because they aren't used much so the stock is always at
minimum (they produce to order). High volume Material like FR4 is a different story, but at 10GBps FR4 is
most often not the best choice.
The differences of dk and df over several production batch is low. The biggest impact on performance is the
thickness variation over several batches. These thickness tolerances can be very high (at least for
thick materials).

If you use the "typical" values of the materials datasheet, AND you calculate for the correct resin
content, then there will be no surprise at the end. If you don't take the resin content into account, you
might be very supprised for some materials (e.g. megtron 6 promotes a very low df, but thats for the very
best resin content, some glass styles make it as lossy as much cheaper materials).

BR
Gert

-----Ursprüngliche Nachricht-----
Von: si-list-bounce@...
[mailto:si-list-bounce@...] Im Auftrag von Nagy István
Gesendet: Donnerstag, 16. August 2012 21:06
An: si-list@...; jeff.loyer@...

(Continue reading)

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Dhamija, Naresh | 9 Aug 2012 21:21

Re: 10 Layer Stackup Recommendation for Board with High speed Signals(SERDES/DDR)

Prasanth,
Can I know the speed of high speed signals and also the length of trace it is routed on board to have an idea of
mode conversion at far end. This will give OR rule out the option of routing HS signal in top/bottom layer OR
with asymmetrical references.

Regards
Naresh
-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On Behalf Of Prashanth Rajappan
Sent: Thursday, August 09, 2012 7:47 PM
To: si-list@...
Subject: [SI-LIST] Re: 10 Layer Stackup Recommendation for Board with High speed Signals(SERDES/DDR)

Hi All,
Thanks for the response.I have added more details as per suggestions .In the link given below ,basic block
diagram and the signal speeds(at max through put) have been given.

http://flickr.com/gp/84656325 <at> N08/jH23r1

My Layer constraint is 10 Layer. 

Bill w.r.t in the board ,one power goes to the entire board area hence it will take up the enitire power plane
.And in the other power plane we would require to provide multiple power signals hence splitting the
plane.Because of that we are not able to give continuous reference to the DDR or any other critical signals
with one power plane .

Also if we dont have much option to spread power over signal layers because of the routing space constraints.

Regarding SERDES signals,the tracks can be routed in TOP and Bottom Layers .Another issue is the length of

(Continue reading)