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Balamanikandan K | 11 Aug 2012 14:39
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VIH(AC)& VIH(DC) DDR3

Hi,
1.  I would like to know the difference and importance of AC & DC Logic
input levels  (VIH(AC)& VIH(DC) ) for single-ended signals in DDR3.

2.   For logic High (input) , should  the signal level be higher than VIH
(AC)min or VIH(DC)min?

3. What is the importance and meaning of VIH(AC 175) and VIH(AC 150)

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Balamanikandan.K

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steve weir | 11 Aug 2012 14:47

Re: VIH(AC)& VIH(DC) DDR3

Timing is specified based on the AC thresholds which are more 
stringent.   175 and 150 refer to mV.

Steve.
On 8/11/2012 5:39 AM, Balamanikandan K wrote:
> Hi,
> 1.  I would like to know the difference and importance of AC & DC Logic
> input levels  (VIH(AC)& VIH(DC) ) for single-ended signals in DDR3.
>
>
> 2.   For logic High (input) , should  the signal level be higher than VIH
> (AC)min or VIH(DC)min?
>
> 3. What is the importance and meaning of VIH(AC 175) and VIH(AC 150)
>

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Hermann Ruckerbauer | 11 Aug 2012 17:09
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Re: VIH(AC)& VIH(DC) DDR3

Hello,

your signals need first to cross the AC level to give the Receiver some
overdrive for fast switching and short input setup times.
Once your receiver is switched the level is allowed to go below the AC
level (min) worst case back to DC (min).
Reason for this definition is the difficult signaling with Point to
Multipoint connections that cause a lot of reflections.

You can close your timing budget either with the VIH AC175 or the VIH
AC150. I would need to check in detail, but there should be different
setup/hold times given if you assume one or the other level (maybe also
just the derating is different...)
So if you can not provide the DRAM enough swing to reach Vref + 175mV
you can also work with Vref + 150mV, but you have to accept worse
setup/Hold times ..

Hermann

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Tesla | 14 Aug 2012 03:13
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Re: VIH(AC)& VIH(DC) DDR3

Hi, All

The timing or voltage requirement on DDR3 signal is refered to pin of chip or die of chip? can not find a
indication in JEDEC's standard.

Tesla.

At 2012-08-11 23:09:50,"Hermann Ruckerbauer" <hermann.ruckerbauer <at> eyeknowhow.de> wrote:
>Hello,
>
>your signals need first to cross the AC level to give the Receiver some
>overdrive for fast switching and short input setup times.
>Once your receiver is switched the level is allowed to go below the AC
>level (min) worst case back to DC (min).
>Reason for this definition is the difficult signaling with Point to
>Multipoint connections that cause a lot of reflections.
>
>You can close your timing budget either with the VIH AC175 or the VIH
>AC150. I would need to check in detail, but there should be different
>setup/hold times given if you assume one or the other level (maybe also
>just the derating is different...)
>So if you can not provide the DRAM enough swing to reach Vref + 175mV
>you can also work with Vref + 150mV, but you have to accept worse
>setup/Hold times ..
>
>Hermann
>
>Our next Events:
>================
>
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Hermann Ruckerbauer | 14 Aug 2012 08:39
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Re: VIH(AC)& VIH(DC) DDR3

All timings are defined at the pin .. because here they are tested and
verified.

Nevertheless I do pad to pad simulations and check the signal at the
pad. But this means, that I do have a doublecounting of package effects.
Effects like package X-talk are included in the timing parameter, and
when included in the simulation they are twice included in your timing
budget. So either the simulation a bit more critical or the doublecount
has to be subtracted in the Timing budged.

Hermann

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Gmane